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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
Rev. 04 -- 21 November 2003 Product data
1. General description
The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC901/902/903 in order to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
s 1 kB byte-erasable Flash code memory organized into 256-byte sectors and 16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. s 128-byte RAM data memory. s Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a port output upon timer overflow or to become a PWM output.) s 23-bit system timer that can also be used as a Real-Time clock. s Two analog comparators (P89LPC902 and P89LPC903, single analog comparator on P89LPC901). s Enhanced UART with fractional baudrate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC903). s High-accuracy internal RC oscillator option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. s 2.4 V to 3.6 V VDD operating range with 5 V tolerant I/O pins (may be pulled up or driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1, 8, and 4. s Up to six I/O pins when using internal oscillator and reset options. s 8-pin SO-8 package.
2.2 Additional features
s A high performance 80C51 CPU provides instruction cycle times of 167 ns to 333 ns for all instructions except multiply and divide when executing at 12 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. s In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
s Serial Flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. s Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values. s Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. s Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 A (total Power-down with voltage comparators disabled). s Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. s Configurable on-chip oscillator with frequency range options selected by user programmed Flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 12 MHz (P89LPC901). s Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from 8 values. s Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. s Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. s LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. s Only power and ground connections are required to operate the P89LPC901/902/903 when internal reset option is selected. s Four interrupt priority levels. s Two (P89LPC901), three (P89LPC903), or five (P89LPC902) keypad interrupt inputs. s Second data pointer. s Schmitt trigger port inputs. s Emulation support.
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Product data
Rev. 04 -- 21 November 2003
2 of 55
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
3. Ordering information
Table 1: Ordering information Package Name P89LPC901FD P89LPC902FD P89LPC903FD P89LPC901FN P89LPC902FN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 SO8 Description plastic small outline package; 8 leads; body width 7.5 mm Version SOT96-1 Type number
3.1 Ordering options
Table 2: Part options Temperature range -40 C to +85 C Frequency 0 to 12 MHz Internal RC or watchdog Internal RC or watchdog Type number P89LPC901xx P89LPC902xx P89LPC903xx
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Product data
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
4. Block diagram
P89LPC901
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
1 kB CODE FLASH INTERNAL BUS 128-BYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os
TIMER 0 TIMER 1 REAL-TIME CLOCK/ SYSTEM TIMER
ANALOG COMPARATOR
PORT 0 CONFIGURABLE I/Os
KEYPAD INTERRUPT
WATCHDOG TIMER AND OSCILLATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
PROGRAMMABLE OSCILLATOR DIVIDER
CPU CLOCK
CRYSTAL OR RESONATOR
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR
002aaa444
Fig 1. P89LPC901 block diagram.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
P89LPC902
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
1 kB CODE FLASH 128-BYTE DATA RAM PORT 1 INPUT INTERNAL BUS
TIMER 0 TIMER 1 REAL-TIME CLOCK/ SYSTEM TIMER
ANALOG COMPARATORS
PORT 0 CONFIGURABLE I/Os
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
PROGRAMMABLE OSCILLATOR DIVIDER
CPU CLOCK
ON-CHIP RC OSCILLATOR
002aaa445
Fig 2. P89LPC902 block diagram.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
P89LPC903
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
1 kB CODE FLASH 128-BYTE DATA RAM PORT 1 INPUT INTERNAL BUS
UART
TIMER 0 TIMER 1 REAL-TIME CLOCK/ SYSTEM TIMER
PORT 0 CONFIGURABLE I/Os
ANALOG COMPARATORS
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
PROGRAMMABLE OSCILLATOR DIVIDER
CPU CLOCK
ON-CHIP RC OSCILLATOR
002aaa446
Fig 3. P89LPC903 block diagram.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
5. Pinning information
5.1 Pinning
handbook, halfpage
XTAL1/P3.1 2 CLKOUT/XTAL2/P3.0 3 RST/P1.5 4
P89LPC901FD
VDD 1
8 7 6 5
VSS P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 P1.2/T0
002aaa438
Fig 4. P89LPC901 pinning (SO8).
handbook, halfpage
P89LPC901FN
VDD 1 XTAL1/P3.1 2 CLKOUT/XTAL2/P3.0 3 RST/P1.5 4
8 VSS 7 P0.4/CIN1A/KBI4 6 P0.5/CMPREF/KBI5 5 P1.2/T0
002aaa469
Fig 5. P89LPC901 pinning (DIP8).
handbook, halfpage
P0.2/CIN2A/KBI2 2 P0.0/CMP2/KBI0 3 RST/P1.5 4
P89LPC902FD
VDD 1
8 7 6 5
VSS P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6
002aaa439
Fig 6. P89LPC902 pinning (SO8).
handbook, halfpage
P0.2/CIN2A/KBI2 2 P0.0/CMP2/KBI0 3 RST/P1.5 4
P89LPC902FN
VDD 1
8 VSS 7 P0.4/CIN1A/KBI4 6 P0.5/CMPREF/KBI5 5 P0.6/CMP1/KBI6
002aaa470
Fig 7. P89LPC902 pinning (DIP8).
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Product data
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
handbook, halfpage
P0.2/CIN2A/KBI2 2 P1.1/RxD 3 RST/P1.5 4
P89LPC903FD
VDD 1
8 7 6 5
VSS P0.4/CIN1A/KBI4 P0.5/CMPREF/KBI5 P1.0/TxD
002aaa440
Fig 8. P89LPC903 pinning (SO8).
5.2 Pin description
Table 3: Symbol P0.0 - P0.6 P89LPC901 pin description Pin 6, 7 Type I/O Description Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 7 I/O I I 6 I/O I I P1.0 - P1.5 4, 5 P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 5 4 I/O O I I P1.2 -- Port 1 bit 2. T0 -- Timer/counter 0 external count input or overflow output. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Table 3: Symbol P3.0 - P3.1
P89LPC901 pin description...continued Pin 2, 3 Type I/O Description Port 3: Port 3 is an I/O port with a user-configurable output types. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: 3 I/O O O P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the real time clock/system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
2
I/O I
VSS VDD
8 1
I I
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Table 4: Symbol P0.0 - P0.6
P89LPC902 pin description Pin 2, 3, 5, 6, 7 Type I/O Description Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 3 I/O I I 2 I/O I I 7 I/O I I 6 I/O I I 5 I/O O I P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output. KBI0 -- Keyboard input 0. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 4 I I P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P1.0 - P1.5
4
VSS VDD
8 1
I I
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Table 5: Symbol P0.0 - P0.6
P89LPC903 pin description Pin 2, 6, 7 Type I/O Description Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: 2 I/O I I 7 I/O I I 6 I/O I I P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "DC electrical characteristics" for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below: 5 3 4 I/O O I/O I I I P1.0 -- Port 1 bit 0. TxD -- Serial port transmitter data. P1.1 -- Port 1 bit 1. RxD -- Serial port receiver data. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P1.0 - P1.5
3, 4, 5
VSS VDD
8 1
I I
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
6. Logic symbols
VDD VSS
PORT 1
PORT 0
CLKOUT
XTAL2 XTAL1
PORT 3
Fig 9. P89LPC901 logic symbol.
VDD
P89LPC901
KBI4 KBI5
CIN1A CMPREF
RST T0
002aaa441
VSS
Fig 10. P89LPC902 logic symbol.
VDD
P89LPC902
KBI4 KBI5 KBI6 KBI2 KBI0
CIN1A CMPREF CMP1 CIN2A CMP2
PORT 1
PORT 0
RST
002aaa442
VSS
PORT 0
KBI4 KBI5 KBI2
CIN1A CMPREF CIN2A
Fig 11. P89LPC903 logic symbol.
P89LPC903
RST RxD TxD
002aaa443
PORT 1
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8-bit microcontrollers with two-clock 80C51 core
Table 6 highlights the differences between these three devices. For a complete list of device features, please see Section 2 "Features" on page 1.
Table 6: Product comparison overview External crystal pins X CLKOUT output T0 PWM output CMP2 input X X X X CMP1 and CMP2 outputs X UART TxD X Rxd X
Type number P89LPC901xx P89LPC902xx P89LPC903xx
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8-bit microcontrollers with two-clock 80C51 core
7. Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
* SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
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Product data Rev. 04 -- 21 November 2003
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Table 7: P89LPC901 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* CMP1 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Comparator 1 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer HIGH Data pointer LOW Program Flash address HIGH Program Flash address LOW Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 HIGH E5H A8H Bit address E8H Bit address B8H B7H Bit address IP1* IP1H KBCON Interrupt priority 1 Interrupt priority 1 HIGH Keypad control register F8H F7H 94H EA EF BF FF EWDRT EE BE PWDRT PWDRT H FE EBO ED BD PBO PBOH FD EC BC FC ET1 EB BB PT1 PT1H FB EA EC BA FA PC PCH ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH PATN _SEL E8 B8 F8 KBIF 00[1] 00[1] 00[1] 00x00000 00x00000 xxxxxx00 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 00 00000000 00000000 00 00 00 00 70 00000000 00000000 00000000 00000000 01110000 E0H A2H F0H ACH 95H CE1 CN1 CO1 CMF1 CLKLP F7 F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00[1] 00 00000000 xx000000 00000000 Bit address Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC901/902/903
15 of 55
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Table 7: P89LPC901 Special function registers...continued * indicates SFRs that are bit addressable. Name KBMASK KBPATN P0* Description Keypad interrupt mask register Keypad pattern register Port 0 SFR addr. 86H 93H Bit address 80H Bit address P1* P3*
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Bit functions and addresses MSB LSB
Reset value Hex 00 FF Binary 00000000 11111111
87 97 B7 RTCPD D7 CY RTCF
86 96 B6 D6 AC RTCS1
85 CMPREF /KB5 95 RST B5 -
84 CIN1A /KB4 94 B4 -
83 93 B3 GF1 D3 RS0 -
82 92 T0 B2 (P1M1.2) (P1M2.2) GF0 D2 OV R_WD -
81 91 B1 XTAL1 -
80 90 B0 XTAL2 [1] [1] [1]
Port 1 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A reserved for Power Control Register B Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register HIGH Real-time clock register LOW Stack pointer Timer 0 auxiliary mode
90H Bit address B0H 84H 85H 91H 92H B1H B2H 87H B5H B6H
P0M1 P0M2 P1M1 P1M2 P3M1 P3M2 PCON PCONA PCONB
(P0M1.5) (P0M1.4) (P0M2.5) (P0M2.4) (P1M1.5) (P1M2.5) BOPD VCPD D5 F0 PT0AD.5 BOF RTCS0 D4 RS1 PT0AD.4 POF BOI
FF 00 FF[1] 00[1] 00[1] 00 00[1] 00[1]
11111111 00000000 11111111 00000000 xxxxxx11 xxxxxx00 00000000 00000000 xxxxxxxx
(P3M1.1) (P3M1.0) 03[1] (P3M2.1) (P3M2.0) PMOD1 D1 F1 R_SF ERTC D0 P R_EX RTCEN 00 00
[3]
8-bit microcontrollers with two-clock 80C51 core
PMOD0
P89LPC901/902/903
Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SP TAMOD D0H F6H DFH D1H D2H D3H 81H 8FH
00000000 xx00000x 011xxx00 00000000 00000000 00000111 xxx0xxx0
60[1]
[6]
00[6] 00[6] 07 T0M2 00
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Table 7: P89LPC901 Special function registers...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
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Bit functions and addresses MSB 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 LSB 88 -
Reset value Hex 00 00 00 00 00 Binary 00000000 00000000 00000000 00000000 00000000 00000000
Timer 0 and 1 control Timer 0 HIGH Timer 1 HIGH Timer 0 LOW Timer 1 LOW Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
PRE2
PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
TRIM.3 -
TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
FF
11111111
[3] [4] [5] [6]
All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable. Unimplemented bits in SFRs (labeled '-') are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are `0's although they are unknown when read. The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
8-bit microcontrollers with two-clock 80C51 core
P89LPC901/902/903
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Product data Rev. 04 -- 21 November 2003
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Philips Semiconductors
Table 8: P89LPC902 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer HIGH Data pointer LOW Program Flash address HIGH Program Flash address LOW Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 HIGH E5H A8H Bit address E8H Bit address B8H B7H Bit address IP1* IP1H Interrupt priority 1 Interrupt priority 1 HIGH F8H F7H EA EF BF FF EWDRT EE BE PWDRT PWDRT H FE EBO ED BD PBO PBOH FD EC BC FC ET1 EB BB PT1 PT1H FB EA EC BA FA PC PCH ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH E8 B8 F8 00[1] 00[1] 00x00000 00x00000 00[1] 00[1] x0000000 x0000000 00[1] 00x00000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 00 00000000 00000000 00 00 00 00 70 00000000 00000000 00000000 00000000 01110000 E0H A2H F0H ACH ADH 95H CE1 CE2 CN1 CN2 OE1 OE2 CO1 CO2 CMF1 CMF2 F7 F6 F5 F4 SRST F3 0 F2 F1 DPS F0 00 00[1] 00[1] 00 00000000 xx000000 xx000000 00000000 Bit address Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC901/902/903
18 of 55
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Table 8: P89LPC902 Special function registers...continued * indicates SFRs that are bit addressable. Name KBCON KBMASK KBPATN P0* Description Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 SFR addr. 94H 86H 93H Bit address 80H Bit address P1*
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Product data 19 of 55
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Bit functions and addresses MSB PATN _SEL LSB KBIF
Reset value Hex 00[1] 00 FF Binary xxxxxx00 00000000 11111111
87 97 B7 RTCPD D7 CY RTCF
86 CMP1 /KB6 96 B6
85 CMPREF /KB5 95 RST B5
84 CIN1A /KB4 94 B4
83 93 B3 GF1 D3 RS0 -
82 KB2 92 B2 (P0M1.2) (P0M2.2) GF0 D2 OV PT0AD.2 R_WD -
81 91 B1 PMOD1 D1 F1 R_SF ERTC
80 KB0 90 B0 (P0M1.0) FF (P0M2.0) 00 PMOD0 D0 P R_EX RTCEN 00 00
[3] [1]
Port 1 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A reserved for Power Control Register B Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register HIGH Real-time clock register LOW Stack pointer
90H Bit address 84H 85H 91H 92H 87H B5H B6H
P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
(P0M1.6) (P0M1.5) (P0M1.4) (P0M2.6) (P0M2.5) (P0M2.4) D6 AC RTCS1 (P1M1.5) (P1M2.5) BOPD VCPD D5 F0 PT0AD.5 BOF RTCS0 D4 RS1 PT0AD.4 POF BOI
11111111 00000000 11111111 00000000
FF[1] 00[1] 00 00[1] 00[1]
8-bit microcontrollers with two-clock 80C51 core
00000000 00000000 xxxxxxxx
P89LPC901/902/903
Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SP D0H F6H DFH D1H D2H D3H 81H
00000000 xx00000x 011xxx00 00000000 00000000 00000111
60[1]
[6]
00[6] 00[6] 07
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Table 8: P89LPC902 Special function registers...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
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Bit functions and addresses MSB 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 LSB 88 -
Reset value Hex 00 00 00 00 00 Binary 00000000 00000000 00000000 00000000 00000000 00000000
Timer 0 and 1 control Timer 0 HIGH Timer 1 HIGH Timer 0 LOW Timer 1 LOW Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
PRE2
PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
TRIM.3 -
TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
FF
11111111
[3] [4] [5] [6]
All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable. Unimplemented bits in SFRs (labeled '-') are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are `0's although they are unknown when read. The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
8-bit microcontrollers with two-clock 80C51 core
P89LPC901/902/903
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Product data Rev. 04 -- 21 November 2003
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Philips Semiconductors
Table 9: P89LPC903 Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 B* BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Baud rate generator rate LOW Baud rate generator rate HIGH Baud rate generator control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer HIGH Data pointer LOW Program Flash address HIGH Program Flash address LOW Program Flash Control (Read) Program Flash Control (Write) FMDATA IEN0* IEN1* IP0* Program Flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 E5H A8H Bit address E8H Bit address B8H EA EF BF EWDRT EE EST BE PWDRT EBO ED BD PBO ES/ESR EC BC PS/PSR ET1 EB BB PT1 EA EC BA ET0 E9 EKBI B9 PT0 E8 B8 00[1] x0000000 00[1] 00x00000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 00 00000000 00000000 00 00 00 00 70 00000000 00000000 00000000 00000000 01110000 E0H A2H F0H BEH BFH BDH ACH ADH 95H CE1 CE2 CN1 CN2 SBRGS CO1 CO2 BRGEN CMF1 CMF2 F7 EBRR F6 F5 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[6] 00[1] 00[1] 00 00000000 00000000 00000000 xxxxxx00 xx000000 xx000000 00000000 Bit address Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00[1] 00000000 000000x0 Reset value Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC901/902/903
21 of 55
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Table 9: P89LPC903 Special function registers...continued * indicates SFRs that are bit addressable. Name IP0H Description Interrupt priority 0 HIGH SFR addr. B7H Bit address IP1* IP1H KBCON KBMASK KBPATN
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Bit functions and addresses MSB FF PWDRT H FE PST PSTH PBOH FD PSH /PSRH FC PT1H FB FA PC PCH PT0H F9 PKBI PKBIH PATN _SEL LSB F8 KBIF
Reset value Hex 00[1] Binary x0000000
Interrupt priority 1 Interrupt priority 1 HIGH Keypad control register Keypad interrupt mask register Keypad pattern register Port 0
F8H F7H 94H 86H 93H Bit address
00[1] 00[1] 00[1] 00 FF
00x00000 00x00000 xxxxxx00 00000000 11111111
87 97 SMOD1 RTCPD D7 CY RTCF
86 96 SMOD0 D6 AC RTCS1
85 CMPREF /KB5 95 RST
84 CIN1A /KB4 94 -
83 93 GF1 D3 RS0 R_BK -
82 KB2 92 (P0M1.2) (P0M2.2) GF0 D2 OV PT0AD.2 R_WD -
81 91 RxD -
80 90 TxD
[1]
P0*
80H Bit address
P1* P0M1 P0M2 P1M1 P1M2 PCON PCONA PCONB
Port 1 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Power control register Power control register A reserved for Power Control Register B Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register HIGH
90H 84H 85H 91H 92H 87H B5H B6H
8-bit microcontrollers with two-clock 80C51 core
(P0M1.5) (P0M1.4) (P0M2.5) (P0M2.4) (P1M1.5) (P1M2.5) BOPD VCPD D5 F0 PT0AD.5 BOF RTCS0 D4 RS1 PT0AD.4 POF BOI
-
FF 00 FF[1] 00[1] 00 00[1] 00[1]
11111111 00000000 11111111 00000000 00000000 00000000 xxxxxxxx
(P1M1.1) (P1M1.0) (P1M2.1) (P1M2.0) PMOD1 SPD D1 F1 R_SF ERTC D0 P R_EX RTCEN PMOD0
P89LPC901/902/903
Bit address PSW* PT0AD RSTSRC RTCCON RTCH D0H F6H DFH D1H D2H
00 00
[3]
00000000 xx00000x 011xxx00 00000000
60[1]
[6]
00[6]
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Table 9: P89LPC903 Special function registers...continued * indicates SFRs that are bit addressable. Name RTCL SADDR SADEN SBUF SCON* SSTAT SP
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Description Real-time clock register LOW Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer Timer 0 and 1 control Timer 0 HIGH Timer 1 HIGH Timer 0 LOW Timer 1 LOW Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
SFR addr. D3H A9H B9H 99H
Bit functions and addresses MSB LSB
Reset value Hex 00[6] 00 00 xx Binary 00000000 00000000 00000000 xxxxxxxx 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000
Bit address 98H BAH 81H Bit address TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
[1] [2]
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 07
8F TF1
8E TR1
8D TF0
8C TR0
8B -
8A -
89 -
88 00 00 00 00 00
88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H
8-bit microcontrollers with two-clock 80C51 core
PRE2
PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
TRIM.3 -
TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
P89LPC901/902/903
FF
11111111
[3] [4] [5] [6]
All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is `0'. If any are written while BRGEN = 1, the result is unpredictable. Unimplemented bits in SFRs (labeled '-') are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are `0's although they are unknown when read. The RSTSRC register reflects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all `1', WDRUN = 1 and WDCLK = 1. WDTOF bit is `1' after Watchdog reset and is `0' after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
8. Functional description
Remark: Please refer to the P89LPC901/902/903 User's Manual for a more detailed functional description.
8.1 Enhanced CPU
The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1 Clock definitions The P89LPC901/902/903 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of the clock sources (see Figures 12, 13, and 14) and can also be optionally divided to a slower frequency (see Section 8.7 "CPU CLOCK (CCLK) modification: DIVM register"). Note: fOSC is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. PCLK -- Clock for the various peripheral devices and is CCLK/2 8.2.2 CPU clock (OSCCLK) The P89LPC901/902/903 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip Watchdog oscillator and an on-chip RC oscillator. The P89LPC901, in addition, includes an option for an oscillator using an external crystal or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz. 8.2.3 Low speed oscillator option (P89LPC901) This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration. 8.2.4 Medium speed oscillator option (P89LPC901) This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
8.2.5
High speed oscillator option (P89LPC901) This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this configuration. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to reduce power consumption. On reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.2.6
Clock output (P89LPC901) The P89LPC901 supports a user selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC901. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.3 On-chip RC oscillator option
The P89LPC901/902/903 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, 2.5%. End-user applications can write to the Trim register to adjust the on-chip RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to reduce power consumption. On reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.4 Watchdog oscillator option
The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option (P89LPC901)
In this configuration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output.
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Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
XTAL1 XTAL2
High freq. Med. freq. Low freq. OSCCLK CCLK
RTC
DIVM
CPU
RC OSCILLATOR (7.3728 MHz) WATCHDOG OSCILLATOR (400 kHz)
2
WDT PCLK TIMERS 0 & 1
002aaa447
Fig 12. Block diagram of oscillator control (P89LPC901).
RTC RC OSCILLATOR (7.3728 MHz)
OSCCLK
DIVM
CCLK
CPU
2
WDT PCLK TIMERS 0 & 1
002aaa448
WATCHDOG OSCILLATOR (400 kHz)
Fig 13. Block diagram of oscillator control (P89LPC902).
RTC RC OSCILLATOR (7.3728 MHz)
OSCCLK
DIVM
CCLK
CPU
2
WATCHDOG OSCILLATOR (400 kHz) PCLK WDT
TIMERS 0 & 1
BAUD RATE GENERATOR
002aaa449
UART
Fig 14. Block diagram of oscillator control (P89LPC903).
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Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
8.6 CPU CLock (CCLK) wake-up delay
The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100 s.
8.7 CPU CLOCK (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
8.8 Low power select
The P89LPC901 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to `1' to lower the power consumption further. On any reset, CLKLP is `0' allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.9 Memory organization
The various P89LPC901/902/903 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.
8.10 Data RAM arrangement
The 128 bytes of on-chip RAM is organized as follows:
Table 10: Type DATA On-chip data memory usages Data RAM Size (Bytes) Memory that can be addressed directly and indirectly 128
8.11 Interrupts
The P89LPC901/902/903 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources.
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect, Watchdog/real-time clock, keyboard, and the comparator. The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect, Watchdog/real-time clock, keyboard, and comparators 1 and 2. The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock, keyboard, and comparators 1 and 2. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 8.11.1 External interrupt inputs The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.14 "Power reduction modes" for details.
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Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
BOPD EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF EC EA (IE0.7) WAKE-UP (IF IN POWER-DOWN)
TF1 ET1
INTERRUPT TO CPU
TF0 ET0
002aaa450
Fig 15. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC901).
BOPD EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF EC EA (IE0.7) WAKE-UP (IF IN POWER-DOWN)
TF1 ET1
INTERRUPT TO CPU
TF0 ET0
002aaa451
Fig 16. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC902).
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P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
BOPD EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 TI & RI/RI ES/ESR TI EST TF0 ET0
002aaa452
WAKE-UP (IF IN POWER-DOWN)
INTERRUPT TO CPU
Fig 17. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC903).
8.12 I/O ports
The P89LPC901 has between 3 and 6 I/O pins: P0.4, P0.5, P1.2, P1.5, P3.0, and P3.1 The exact number of I/O pins available depends on the clock and reset options chosen, as shown in Table 11.
Table 11: Number of I/O pins available Reset option No external reset (except during power-up) External RST pin supported External clock input Low/medium/high speed oscillator (external crystal or resonator) No external reset (except during power-up) External RST pin supported No external reset (except during power-up) External RST pin supported Number of I/O pins (8-pin package) 6 5 5 4 4 3
Clock source On-chip oscillator or Watchdog oscillator
The P89LPC902 and P89LPC903 devices have either 5 or 6 I/O pins depending on the reset pin option chosen. 8.12.1 Port configurations All but one I/O port pin on the P89LPC901/902/903 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured.
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8.12.2
Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.3
Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic `0'. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.4
Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.5
Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic `1'. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.
8.12.6
Port 0 analog functions The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described in Section 8.12.4 "Input-only configuration". Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to `0's to enable digital functions.
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8.12.7
Additional port features After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.
* After power-up all I/O pins, except P1.5, may be configured by software. * Pin P1.5 is input only.
Every output on the P89LPC901/902/903 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 13 "DC electrical characteristics" for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC901/902/903 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect. 8.13.1 Brownout detection The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however, it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the operating voltage range for VDD is 2.7 V to 3.6 V, and the brownout condition occurs when VDD falls below the brownout trip voltage, VBO (see Table 13 "DC electrical characteristics"), and is negated when VDD rises above VBO. If brownout detection is disabled, the operating voltage range for VDD is 2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 13 "DC electrical characteristics" for specifications. 8.13.2 Power-on detection The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
8.14 Power reduction modes
The P89LPC901/902/903 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.
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8.14.1
Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
8.14.2
Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC901/902/903 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down. These include: Brownout detect, Watchdog Timer, Comparators (note that Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
8.14.3
Total Power-down mode This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power-down.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to `1', enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Remark: During a power cycle, VDD must fall below VPOR (see Table 13 "DC electrical characteristics") before power is reapplied, in order to ensure a power-on reset.
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Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1) Power-on detect Brownout detect Watchdog Timer Software reset UART break character detect reset (P80LPC903).
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a `0' to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* For any other reset, previously set flag bits that have not been cleared will remain
set.
8.16 Timers/counters 0 and 1
The P89LPC901/902/903 has two general purpose timers which are similar to the standard 80C51 Timer 0 and Timer 1. These timers have four operating modes (modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different. 8.16.1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1. 8.16.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 8.16.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 8.16.4 Mode 3 When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator. 8.16.5 Mode 6 (P89LPC901) In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
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8.16.6
Timer overflow toggle output (P89LPC901) Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
8.17 Real-Time clock/system timer
The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all `0's, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state.
8.18 UART (P89LPC903)
The P89LPC903 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC903 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16. 8.18.1 Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency. 8.18.2 Mode 1 10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical `0'), 8 data bits (LSB first), and a stop bit (logical `1'). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.18.5 "Baud rate generator and selection"). 8.18.3 Mode 2 11 bits are transmitted (through TxD) or received (through RxD): start bit (logical `0'), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical `1'). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of `0' or `1'. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
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8.18.4
Mode 3 11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical `0'), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical `1'). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in section Section 8.18.5 "Baud rate generator and selection").
8.18.5
Baud rate generator and selection The P89LPC903 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 18). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK.
Timer 1 Overflow (PCLK-based) Baud Rate Generator (CCLK-based)
SMOD1 = 1
SBRGS = 0 Baud Rate Modes 1 and 3
2
SMOD1 = 0
SBRGS = 1
002aaa419
Fig 18. Baud rate sources for UART (Modes 1, 3).
8.18.6
Framing error Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is `1', framing errors can be made available in SCON.7, respectively. If SMOD0 is `0', SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is `0'.
8.18.7
Break detect Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device.
8.18.8
Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = `0'), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = `0').
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8.18.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3) Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.
8.18.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3) If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
8.19 Analog comparators
One analog comparator is provided on the P89LPC901. Two analog comparators are provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such that the output is a logical one (which may be read in a register) when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The comparator may be configured to cause an interrupt when the output value changes. The connections to the comparator are shown in Figure 19. Note: Not all possible comparator configurations are available on all three devices. Please refer to the Logic diagrams in Section 6 "Logic symbols" on page 12. The comparator functions to VDD = 2.4 V. When the comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator's output, COx, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.
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Comparator 1 (P0.4) CIN1A CO1 (P0.5) CMPREF VREF CN1
OE1
CMP1 (P0.6)
Change Detect CMF1
Interrupt Change Detect Comparator 2 (P0.2) CIN2A CMP2 (P0.0) CO2 OE2 CN2
002aaa453
EC CMF2
Fig 19. Comparator input and output connections.
8.20 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as VREF, is 1.23 V 10%.
8.21 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt.
8.22 Comparator and power reduction modes
The comparators may remain enabled when Power-down or Idle mode is activated, but the comparators are disabled automatically in Total Power-down mode. If the comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. The comparator consumes power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparator via PCONA.5 or put the device in Total Power-down mode.
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8.23 Keypad interrupt (KBI)
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.
8.24 Watchdog timer
The Watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer can only be reset by a power-on reset. When the Watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 20 shows the Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down, the watchdog is disabled. The Watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC901/902/903 User's Manual for more details.
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WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog oscillator PCLK
/32
PRESCALER
8-BIT DOWN COUNTER
RESET see note (1)
CONTROL REGISTER
SHADOW REGISTER FOR WDCON
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa423
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = `1').
8.25 Additional features
8.25.1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or Watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets. 8.25.2 Dual data pointers The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic `0' so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
8.26 Flash program memory
8.26.1 General description The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and programming. The Flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. In-Circuit Programming using standard commercial programmers is available. In addition, In-Application Programming (IAP) and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC901/902/903 Flash reliably stores memory contents even after more than 100,000 erase and program cycles. The cell is
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designed to optimize the erase and programming mechanisms. The P89LPC901/902/903 uses VDD as the supply voltage to perform the Program/Erase algorithms. 8.26.2 Features
* * * * * * * *
8.26.3
Programming and erase over the full operating voltage range. Byte-erase allowing code memory to be used for data storage. Read/Programming/Erase using ICP. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the Flash for each sector. More than 100,000 minimum erase/program cycles for each byte. 10-year minimum data retention.
Flash organization The P89LPC901/902/903 program memory consists of four 256 byte sectors. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported.
8.26.4
Flash programming and erasing Different methods of erasing or programming of the Flash are available. The Flash may be programmed or erased in the end-user application (IAP) under control of the application's firmware. Another option is to use the In-Circuit Programming (ICP) mechanism. This ICP system provides for programming through a serial clock- serial data interface. Third, the Flash may be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 1 KB of user code space.
8.26.5
In-circuit programming (ICP) In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC901/902/903 through a two-wire serial interface. The Philips In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC901/902/903 User's Manual.
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8.26.6
In-application programming In-Application Programming is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The Philips In-Application Programming has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC901/902/903 User's Manual.
8.26.7
Using flash as data storage The Flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
8.26.8
User configuration bytes Some user-configurable features of the P89LPC901/902/903 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the Flash byte UCFG1. Please see the P89LPC901/902/903 User's Manual for additional details.
8.26.9
User sector security bytes There are four User Sector Security Bytes, each corresponding to one sector. Please see the P89LPC901/902/903 User's Manual for additional details.
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8-bit microcontrollers with two-clock 80C51 core
9. Limiting values
Table 12: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Tamb(bias) Tstg Vxtal Vn IOH(I/O) IOL(I/O) II/O(tot)(max) Ptot(pack) Parameter operating bias ambient temperature storage temperature range voltage on XTAL1, XTAL2 pin to VSS, as applicable voltage on any other pin to VSS HIGH-level output current per I/O pin LOW-level output current per I/O pin maximum total I/O current total power dissipation per package based on package heat transfer, not device power consumption Conditions Min -55 -65 -0.5 Max +125 +150 VDD + 0.5 +5.5 8 20 120 1.5 Unit C C V V mA mA mA W
[1]
[2] [3]
Stresses above those listed under Table 12 "Limiting values" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in Table 13 "DC electrical characteristics" and Table 14 "AC characteristics" section of this specification are not implied. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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10. Static characteristics
Table 13: DC electrical characteristics VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol IDD IID IDD Parameter power supply current, operating (P89LPC901) power supply current, Idle mode (P89LPC901) power supply current, operating (P89LPC902, P89LPC903) power supply current, Idle mode (P89LPC902, P89LPC903) Power supply current, Power-down mode, voltage comparators powered-down Power supply current, Total Power-down mode VDD rise time VDD fall time Power-on reset detect voltage RAM keep-alive voltage negative-going threshold voltage (Schmitt input) positive-going threshold voltage (Schmitt input) hysteresis voltage LOW-level output voltage; all ports, all modes except Hi-Z IOL = 20 mA IOL = 10 mA IOL = 3.2 mA VOH HIGH-level output voltage, all ports IOH = -8 mA; push-pull mode IOH = -3.2 mA; push-pull mode IOH = -20 A; quasi-bidirectional mode Cio IIL ILI ITL RRST input/output pin capacitance logical 0 input current, all ports logical 1-to-0 transition current, all ports internal reset pull-up resistor VIN = 0.4 V
[6] [5]
Conditions 3.6 V; 12 MHz 3.6 V; 12 MHz 3.6 V; 7.373 MHz
[7]
Min -
Typ[1] 11 1 7
Max 18 4
Unit mA mA mA
[7]
[8]
IID
3.6 V; 7.373 MHz
[8]
-
1

mA
IPD
3.6 V
[7][8]
-
-

A
IPD1 VDDR VDDF VPOR VRAM Vth(HL) Vth(LH) Vhys VOL
3.6 V
[7][8]
1.5 0.22VDD VDD - TBD VDD - 0.7 VDD - 0.3 -30 10
1 0.4VDD 0.6VDD 0.2VDD 0.6 0.3 0.2 VDD - 0.4 VDD - 0.2 -
5 2 50 0.2 0.7VDD 1.0 0.5 0.3 15 -80 10 -450 30
A mV/s mV/s V V V V V V V V V V V pF A A A k
input leakage current, all ports VIN = VIL or VIH VIN = 2.0 V at VDD = 3.6 V
[4] [2][3]
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8-bit microcontrollers with two-clock 80C51 core
Table 13: DC electrical characteristics...continued VDD = 2.4 V to 3.6 V unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol VBO VREF TC(VREF) Parameter brownout trip voltage with BOV = `1', BOPD = `0' bandgap reference voltage bandgap temperature coefficient Conditions 2.4 V < VDD < 3.6 V Min 2.40 1.11 Typ[1] 1.23 10 Max 2.70 1.34 20 Unit V V ppm/ C
[1] [2] [3] [4] [5] [6] [7] [8]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) Port pins source a transition current when used in quasi-bidirectional mode and externally driven from `1' to `0'. This current is highest when VIN is approximately 2 V. Measured with port in high-impedance mode. Measured with port in quasi-bidirectional mode. Pin capacitance is characterized but not tested. The IDD, IPD specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and Watchdog timer (P89LPC901). The IDD, IPD specifications are measured with the following functions disabled: comparators, brownout detect, and Watchdog timer (P89LPC902, P89LPC903).
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8-bit microcontrollers with two-clock 80C51 core
11. Dynamic characteristics
Table 14: AC characteristics Tamb = -40 C to +85 C for industrial, unless otherwise specified.[1] Symbol fRCOSC Parameter internal RC oscillator frequency (nominal f = 7.3728 MHz) trimmed to 1% at Tamb = 25 C internal Watchdog oscillator frequency (nominal f = 400 kHz) oscillator frequency clock cycle CLKLP active frequency glitch rejection, P1.5/RST pin signal acceptance, P1.5/RST pin glitch rejection, any pin except P1.5/RST signal acceptance, any pin except P1.5/RST External clock (P89LPC901) tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tDVXH
[1] [2]
Conditions
Variable clock Min 7.189 Max 7.557
fOSC = 12 MHz Min 7.189 Max 7.557
Unit MHz
fWDOSC
280
480
280
480
kHz
Crystal oscillator (P89LPC901) fOSC tCLCL fCLKP Glitch filter 125 50 50 15 125 50 50 15 ns ns ns ns 0 see Figure 22 83 0 12 8 MHz ns MHz
HIGH time LOW time rise time fall time serial port clock cycle time output data set-up to clock rising edge output data hold after clock rising edge input data hold after clock rising edge
see Figure 22 see Figure 22 see Figure 22 see Figure 22 see Figure 21 see Figure 21 see Figure 21 see Figure 21
33 33 16 tCLCL 13 tCLCL 150
tCLCL - tCLCX tCLCL - tCHCX 8 8 tCLCL + 20 0 -
33 33 1333 1083 150
8 8 103 0 -
ns ns ns ns ns ns ns ns ns
Shift register (UART mode 0 - P89LPC903)
input data valid to clock rising edge see Figure 21
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontrollers with two-clock 80C51 core
tXLXL Clock tQVXH Output Data 0 Write to SBUF Input Data Clear RI Set RI
002aaa425
tXHQX 1 tXHDX Set TI
Valid Valid Valid Valid Valid Valid Valid Valid
2
3
4
5
6
7
tXHDV
Fig 21. Shift register mode timing.
VDD - 0.5 V 0.45 V
0.2 VDD + 0.9 0.2 VDD - 0.1 V tCHCX
tCHCL
tCLCX
tC
tCLCH
002aaa416
Fig 22. External clock timing.
12. Comparator electrical characteristics
Table 15: Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, unless otherwise specified. Symbol VIO VCR CMRR Parameter offset voltage comparator inputs common mode range comparator inputs common mode rejection ratio response time comparator enable to output valid IIL
[1]
[1]
Conditions
Min 0 -
Typ 250 -
Max 20 VDD - 0.3 -50 500 10 10
Unit mV V dB ns s A
input leakage current, comparator
0 < VIN < VDD
-
This parameter is characterized, but not tested in production.
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13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 pin 1 index Lp 1 e bp 4 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
0.028 0.004 0.012
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 23. SOT96-1
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8-bit microcontrollers with two-clock 80C51 core
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D seating plane
ME
A2
A
L
A1
c Z e b1 wM (e 1) b2 5 MH
b 8
pin 1 index E
1
4
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 24. SOT97-1
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14. Soldering
14.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.
14.2 Through-hole mount packages
14.2.1 Soldering by dipping or by solder wave Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
14.3 Surface mount packages
14.3.1 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all the BGA and SSOP-T packages
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- for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.3.3 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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14.4 Package related soldering information
Table 16: Mounting Through-hole mount Through-holesurface mount Surface mount Suitability of IC packages for wave, reflow and dipping soldering methods Package[1] DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[4] BGA, LBGA, LFBGA, SQFP, SSOP-T[5], TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP
[1] [2]
Soldering method Wave suitable[3] not suitable not suitable Reflow[2] - Dipping suitable
- suitable -
not suitable[6]
suitable
-
suitable not not recommended[7][8] recommended[9]
suitable suitable suitable
- - -
[3] [4] [5]
[6]
[7] [8] [9]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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15. Revision history
Table 17: Rev Date 04 20031121 Revision history CPCN Description Product data (9397 750 12293); ECN 853-2434 01-A14555 of 18 November 2003 Modifications:
* * * * * * * * * *
03 02 01 20030929 20030731 20030602 -
Changed CIN to CIN1A throughout document. Changed CMP to CMP1 throughout document. Figure 1 "P89LPC901 block diagram." on page 4; adjusted drawing. Figure 2 "P89LPC902 block diagram." on page 5; adjusted drawing. Figure 3 "P89LPC903 block diagram." on page 6; adjusted drawing. Table 5 "P89LPC903 pin description" on page 11; changed CIN to CIN1A. Table 8 "P89LPC902 Special function registers" on page 18; removed ENCLK Table 9 "P89LPC903 Special function registers" on page 21; removed ENCLK Figure 19 "Comparator input and output connections." on page 38; adjusted drawing. Table 13 "DC electrical characteristics" on page 44; changed ITL VIN value from 1.5 V to 2.0 V.
Product data (9397 750 12031); ECN 853-2434 30348 of 11 September 2003 Product data (9397 750 11801); ECN 853-2434 30152 of 28 July 2003 Preliminary data (9397 750 11494)
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16. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
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8-bit microcontrollers with two-clock 80C51 core
Contents
1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 9 10 11 12 13 14 14.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 12 Special function registers . . . . . . . . . . . . . . . . 14 Functional description . . . . . . . . . . . . . . . . . . 24 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 24 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 On-chip RC oscillator option . . . . . . . . . . . . . . 25 Watchdog oscillator option . . . . . . . . . . . . . . . 25 External clock input option (P89LPC901) . . . . 25 CPU CLock (CCLK) wake-up delay . . . . . . . . 27 CPU CLOCK (CCLK) modification: DIVM register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Low power select . . . . . . . . . . . . . . . . . . . . . . 27 Memory organization . . . . . . . . . . . . . . . . . . . 27 Data RAM arrangement . . . . . . . . . . . . . . . . . 27 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power monitoring functions. . . . . . . . . . . . . . . 32 Power reduction modes . . . . . . . . . . . . . . . . . 32 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 34 Real-Time clock/system timer. . . . . . . . . . . . . 35 UART (P89LPC903) . . . . . . . . . . . . . . . . . . . . 35 Analog comparators . . . . . . . . . . . . . . . . . . . . 37 Internal reference voltage . . . . . . . . . . . . . . . . 38 Comparator interrupt. . . . . . . . . . . . . . . . . . . . 38 Comparator and power reduction modes . . . . 38 Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . 39 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 39 Additional features . . . . . . . . . . . . . . . . . . . . . 40 Flash program memory. . . . . . . . . . . . . . . . . . 40 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43 Static characteristics. . . . . . . . . . . . . . . . . . . . 44 Dynamic characteristics . . . . . . . . . . . . . . . . . 46 Comparator electrical characteristics . . . . . . 47 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.2 14.3 14.4 15 16 17 18 Through-hole mount packages . . . . . . . . . . . Surface mount packages . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 50 52 53 54 54 54
(c) Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 21 November 2003 Document order number: 9397 750 12293

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